One method for determining the current through a load in a circuit is to use a metal oxide semiconductor field effect transistor (MOSFET) for current sensing. Current sensing power MOSFETs conventionally include several thousand transistor cells arranged in parallel and sharing common drain, source and gate electrodes. Each transistor cell or element within the device is identical and current applied at the drain terminal of the device is shared equally between them. In such designs, it is common that the source electrodes of several of the transistors are separated from the remaining source electrodes and connected to a separate source terminal. Accordingly, the resulting current sensing MOSFETs can be thought of as equivalent to two or more transistors in parallel having common gate and drain terminals, but separate source terminals. The first of these transistors, including the majority of the transistor cells in the current sensing power MOSFET, is commonly referred to as the main FET. The second, including the several transistor cells having a separate source terminal, is referred to as the sense FET.
In use, the sense FET conducts only a small fraction of current applied to the common drain terminal, the fraction being inversely proportional to a sense ratio, n, which is a current ratio dependent on the ratio of the number of transistor cells in the main FET to those in the sense FET. The sense ratio n is defined for a condition in which the source terminals of the sense and main FETs are held at the same potential. When the sense ratio is known, the total current flowing through the device, and therefore the load current of a load to which the device is connected, can be calculated from a measurement of the source current of the sense FET, i.e. the current flowing in the current path of the sense FET, between the drain and source electrodes.
However, the wire bonding between the sense FET and the main FET will affect the performance of the device. Furthermore, it would be desirable to develop a power device integrating one or multiple sense FETs into one discrete power MOSFET, in a manner which does not increase number of mask layers and manufacturing process sequences. It is within this context that embodiments of the present invention arise.